(1) Field of the Invention
This invention relates to semiconductor manufacturing, and more particularly to an integrated process for forming a four-transistor SRAM (Static Random Access Memory) and floating gate memory cells on the same integrated circuit (IC).
(2) Description of the Related Art
Two of the major classifications of devices manufactured by the semiconductor industry are logic and memory. Logic devices are used primarily to process information, while memory devices are used for information storage. Traditionally, while these two device types are found in virtually all electronic systems, such as computers and the like, they have been manufactured on separate integrated circuits and connected only at the card or board level. This has been due to differences in manufacturing processes, cost considerations, economies of scale, and other difficulties in fabricating the different device structures on the same substrate.
However, trends in the semiconductor industry are driving toward making it both desirable and feasible to blend memories and logic on the same integrated circuit (IC). Cost and performance are two of the factors contributing to these trends. While significant economies of scale can be realized by the separate batch processing of large numbers of semiconductor wafers for the two types of device, due to the different process steps needed to produce them, cost savings may also be realized by forming logic and memories on the same integrated circuit. For example, due to the decreased amount of chip area required for a blended logic/memory IC, as compared to the area needed on separate IC's, the product yield can be increased, saving manufacturing cost.
Performance enhancements may also make blending logic and memories on the same IC attractive for particular applications. In electronic systems in which logic and memory are packaged separately, data signals between the two may have to pass through several levels of packaging, i.e., through the originating IC chip to external pins, then through card and/or board wiring, and finally into the receiving IC including its internal wiring, all of which cause undesirable propagation delays. As device densities have increased and device sizes have decreased, transistor switching speeds no longer limit the logic delay or access time of the IC. Rather, the time for the device to charge capacitive loads is the limiting factor for IC performance. The capacitive load is partially dependent on the length of lines interconnecting devices, and so minimizing these connection lengths, as through combining logic and memory on the same IC, will enhance performance.
The applications for blending memory and logic on the same IC are varied, and increasing. See "Silicon Processing for the VLSI Era", Volume 2, Process Integration, S. Wolf, pp. 571-572. Some applications add special logic circuits to memory designs, while others add memory structures to primarily logic IC's.
One example of blending technologies is the formation of both bipolar and CMOS device structures on the same chip, for example as disclosed in U.S. Pat. No. 5,066,602 (Takemoto) and U.S. Pat. No. 5,340,762 (Vora), but the process technology to simultaneously form MOS logic and memories is not discussed.
An example of the addition of memory structures to logic IC's is the Intel 80486 microprocessor, which in addition to the main processor logic has an embedded SRAM (Static Random Access Memory) used as a first-level cache. It may also be desirable to form more than one type of memory structure on the same IC, such as an SRAM in conjunction with an EEPROM (Electrically Eraseable Programmable Read Only Memory), as well as logic devices. However, such an IC is difficult to fabricate due to differences in the typical processes for forming memory and logic and for forming significantly different memory devices.
For example, the salicide (self-aligned silicide) process is used in forming MOS transistors in logic devices, to provide self-aligned, low-resistance source/drain contacts. After the gate oxide and polysilicon gate are formed, and after source/drain ion implantation, a layer of reactive metal such as titanium, cobalt or the like is deposited and annealed. During the anneal, the metal reacts with the silicon to form a silicide, such as TiSi.sub.2 (titanium silicide), over the source and drain regions, providing a lower resistance contact than that of the diffused junction alone, which has been shown to be especially valuable as IC feature sizes have been reduced below 1 micrometer. However, the salicide process must be modified for a floating-gate memory, since two layers of polysilicon are required with a thin tunnel oxide formed between the two layers of polysilicon. A floating-gate memory is one of several structures used to in the manufacture of EEPROMs.
A Static RAM, or SRAM, of the prior art is shown in FIG. 1. Depicted is one memory cell of a poly-load, or 4T (four transistor), SRAM in which load devices R1 and R2 are high resistance-value resistors. Access transistors N3 and N4 are NMOS devices whose states are controlled by wordline WL, and when conducting connect the bit lines BL1 and BL2 to the main storage element, the flip-flop circuit of NMOS devices N1 and N2.
Typically, buried contacts are used at nodes Q1 and Q2 to connect the doped polysilicon gate electrodes of devices N1 and N2 to the source/drains of access transistors N3 and N4--this connection is commonly referred to as a local interconnect.